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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 1995-2005, zarlink semiconductor inc. all rights reserved. features ? wide dynamic range (50 db) dtmf receiver ? call progress (cp) detection via cadence indication ? 4-bit synchronous serial data output ? software controlled guard time for mt3x70b ? internal guard time circuitry for mt3x71b ? powerdown option (mt317xb & mt337xb) ? 4.194304 mhz crystal or ceramic resonator (mt337xb and mt327xb) ? external clock input (mt317xb) ? guarantees non-detection of spurious tones applications ? integrated telephone answering machine ? end-to-end signalling ?fax machines august 2005 ordering information mt3170/71be 8 pin pdip tubes mt3270/71be 8 pin pdip tubes mt3370/71bs 18 pin soic tubes mt3370/71bn 20 pin ssop tubes mt3370/71bsr 18 pin soic tape & reel mt3371bnr 20 pin ssop tape & reel mt3270/71be1 8 pin pdip* tubes mt3171be1 8 pin pdip* tubes mt3170be1 8 pin pdip** tubes mt3370/bn1 20 pin ssop* tubes mt3370/71bs1 18 pin soic* tubes mt3370/71bsr1 18 pin soic* tape & reel *pb free matte tin **pb free tin/silver/copper -40 c to 85 c mt3170b/71b, mt3270b /71b, mt3370b/71b wide dynamic range dtmf receiver data sheet figure 1 - functional block diagram pwdn vdd vss input osc2 osc1 (clk) ? mt3170b/71b and mt337xb only. ? mt3270b/71b and mt337xb only. voltage bias circuit agc anti- alias filter high group filter low group filter steering circuit digital detector algorithm code converter and latch digital guard time ? parallel to serial converter & latch mux energy detection oscillator and clock circuit to all chip clocks dial tone filter est dstd ack sd ? ? or ? mt3x71b only.
mt3170b/71b, mt3270b /71b, mt3370b/71b data sheet 2 zarlink semiconductor inc. description the mt3x7xb is a family of high performance dtmf receiv ers which decode all 16 tone pairs into a 4-bit binary code. these devices incorporate an agc for wide dynam ic range and are suitable for end-to-end signalling. the mt3x70b provides an early steering (est) logic output to indicate the detection of a dtmf signal and requires external software guard time to validate the dtmf digit. the mt3x71b, with preset internal guard times, uses a delay steering (dstd) logic output to in dicate the detection of a valid dtmf di git. the 4-bit dtmf binary digit can be clocked out synchronously at the serial data (sd) output . the sd pin is multiplexed with call progress detector output. in the presence of supervisory tones, the call prog ress detector circuit indicate s the cadence (i.e., envelope) of the tone burst. the cadence information can then be proc essed by an external microc ontroller to identify specific call progress signals. the mt327xb and mt337xb can be used with a crystal or a ceramic resonator without additional components. a power-down option is provided for the mt317xb and mt337xb. figure 2 - pin connections pin description pin # name description 337xb 327xb 317xb 2 1 1 input dtmf/cp input. input signal must be ac coupled via capacitor. 42 -osc2 oscillator output. 63 3osc1 (clk) oscillator/clock input. this pin can either be driven by: 1) an external digital clock with defined input logic levels. osc2 should be left open. 2) connecting a crystal or cera mic resonator between osc1 and osc2 pins. 94 4v ss ground. (0v) 11 5 5 sd serial data/call progress output. this pin serves the dual function of being the serial data output wh en clock pulses are applied after validation of dtmf signal, and also indicates the cadence of call progress input. as dtmf signal lies in the same frequency band as call progress signal, this pin may t oggle for dtmf input. the sd pin is at logic low in powerdown state. 13 6 6 ack acknowledge pulse input. after est or dstd is high, applying a sequence of four pulses on this pin w ill then shift out four bits on the sd pin, representing the decoded dt mf digit. the rising edge of the first clock is used to latch the 4-bit data prior to shifting. this pin is pulled down internally. the idle state of the ack signal should be low. 10 18 17 16 15 14 13 12 11 vdd nc nc est/dstd nc ack nc sd nc 1 2 3 4 5 6 7 8 9 nc input pwdn osc2 nc osc1 nc nc vss input pwdn clk vss vdd ack sd input osc2 osc1 vss vdd est/ ack sd mt3170b/71b mt3270b/71b mt3370b/71b 8 pin plastic dip 18 pin plastic soic 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 nc nc input pwdn nc nc osc1 osc2 vss 20 pin ssop nc vdd nc nc ack sd nc nc est/dstd dstd est/ dstd mt3370b/71b nc nc
mt3170b/71b, mt3270b /71b, mt3370b/71b data sheet 3 zarlink semiconductor inc. functional description the mt3x7xbs are high performance and low power cons umption dtmf receivers. these devices provide wide dynamic range dtmf detection and a serial decoded da ta output. these devices also incorporate an energy detection circuit. an input voiceband signal is applied to th e devices via a series decoupling capacitor. following the unity gain buffering, the signal enters the agc circuit fo llowed by an anti-aliasing filter. the bandlimited output is routed to a dial tone filter stage and to the input of the energy detection circuit. a b andsplit filter is then used to separate the input dtmf signal into high and low group tones. the high group and low group tones are then verified and decoded by the internal frequency counting and dtmf detection circuitry. following the detection stage, the valid dtmf digit is translated to a 4-bit binary code (via an internal look-up rom). data bits can then be shifted out serially by applying external clock pulses. automatic gain control (agc) circuit as the device operates on a single power supply, the input signal is biased inte rnally at approxim ately vdd/2. with large input signal amplitude (between 0 and approximately -30 dbm for each tone of the composite signal), the 15 7 7 est (mt3x70b) dstd (mt3x71b) early steering output. a logic high on est indicates that a dtmf signal is present. est is at logic low in powerdown state. delayed steering output. a logic high on dstd indicates that a valid dtmf digit has been detected. dstd is at logic low in powerdown state. 18 8 8 v dd positive power supply (5 v typ.) performance of the device can be optimized by minimizing noise on the supply rails. decoupling capacitors across v dd and v ss are therefore recommended. 1,5,7,8, 10, 12, 14,16, 17 --nc no connection. pin is unconnected internally. 3- 2pwdn power down input. a logic high on this pin will power down the device to reduce power consumption. this pin is pulled down internally and can be left open if no t used. ack pin should be at logic ?0? to power down device. summary of mt3x70/71b product family device type 8 pin 18 pin 20 pin pwdn 2 pin osc ext clk est dstd mt3170b ??? mt3171b ??? mt3270b ?? mt3271b ??? mt3370b ????? mt3371b ???? pin description pin # name description 337xb 327xb 317xb
mt3170b/71b, mt3270b /71b, mt3370b/71b data sheet 4 zarlink semiconductor inc. agc is activated to prevent the input si gnal from being clipped. at low input level, the agc remains inactive and the input signal is passed directly to the hardware dtmf detection algorithm and to the energy detection circuit. filter and decoder section the signal entering the dtmf detec tion circuitry is filtered by a notch filter at 350 and 440 hz for dial tone rejection. the composite dual-tone signal is fu rther split into its individual high and low frequency components by two 6 th order switched capacitor bandpass filters. the high group and low group tones are then smoothed by separate output filters and squared by high gain limiting comparat ors. the resulting squarewav e signals are applied to a digital detection circuit where an aver aging algorithm is employed to deter mine the valid dtmf signal. for mt3x70b, upon recognition of a valid frequency from each t one group, the early steering (est) output will go high, indicating that a dtmf t one has been detected. any subs equent loss of dtmf signal condition will cause the est pin to go low. for mt3x71b, an internal delayed steer ing counter validates the ear ly steering signal after a predetermined guard time which requires no external co mponents. the delayed steering (dstd) will go high only when the validation period has elapsed. once the dstd output is high, the subsequent loss of early steering signal due to dtmf signal dropout w ill activate the inter nal counter for a validation of tone absent guard time. the dstd output will go low only after this validation period. energy detection the output signal from the agc circuit is also applied to the energy detection circuit. the detection circuit consists of a threshold comparator and an acti ve integrator. when the signal level is above the threshold of the internal comparator (-35dbm), the energy detector produces an energy present indication on the sd output. the integrator ensures the sd output will remain at high even though the in put signal is changing. when the in put signal is removed, the sd output will go low following the inte grator decay time. short decay time enables the signal envelope (or cadence) to be generated at the sd output. an external microcon troller can monitor this output for specific call progress sign als. since presence of speech and dtmf si gnals (above the threshold limit) can cause the sd output to toggle, both est (dstd) and sd outputs should be monitored to ensure correct signal identification. as the energy detector is multiplexed wi th the digital serial data output at t he sd pin, the detecto r output is selected at all times except during the time between the rising edge of the first pulse and the falling edge of the fourth pulse applied at the ack pin. serial data (sd) output when a valid dtmf signal burst is present, est or dstd will go high. the application of four clock pulses on the ack pin will provide a 4-bit serial bi nary code representing the decoded dtmf digit on the sd pin output. the rising edge of the first pulse applied on the ack pin latches and shifts the least significant bit of the decoded digit on the sd pin. the next three pulses on ack pin will shift the remain ing latched bits in a serial format (see figure 5). if less than four pulses are applied to the ack pin, new data cannot be latched even though est/dstd can be valid. clock pulses should be applied to clock out any remaining data bits to resume normal operation. any transitions in excess of four pulses will be ignored until th e next rising edge of the est/dstd. ac k should idle at logic low. the 4-bit binary representing all 16 standard dt mf digits are shown in table 1. f low f high digit b 3 b 2 b 1 b 0 697 1209 1 0 0 0 1 697 1336 2 0 0 1 0 697 1477 3 0 0 1 1 770 1209 4 0 1 0 0 770 1336 5 0 1 0 1 770 1477 6 0 1 1 0 852 1209 7 0 1 1 1
mt3170b/71b, mt3270b /71b, mt3370b/71b data sheet 5 zarlink semiconductor inc. 0= logic low, 1= logic high table 1 - serial decode bit table note: b0=lsb of decoded dtmf digit and shifted out first. powerdown mode (mt317xb/337xb) the mt317xb/337xb devices offer a powerdown function to preserve power consumption when the device is not in use. a logic high can be applied at the pwdn pin to place the device in po werdown mode. the ack pin should be kept at logic low to avoid undefined est/dstd and sd outputs (see table 2). table 2 - powerdown mode + =enters powerdown mode on the rising edge. table 3 - call progress tones 852 1336 8 1 0 0 0 852 1477 9 1 0 0 1 941 1336 0 1 0 1 0 941 1209 * 1 0 1 1 941 1477 # 1 1 0 0 697 1633 a 1 1 0 1 770 1633 b 1 1 1 0 852 1633 c 1 1 1 1 941 1633 d 0 0 0 0 ack (input) pwdn (input) est/dstd (output) sd (output) mt317xb/337xb status low low refer to fig. 4 for timing waveforms refer to fig. 4 for timing waveforms normal operation low high + low low powerdown mode high low low undefined undefined high high undefined undefined undefined frequency 1 (hz) frequency 2 (hz) on/off description 350 440 continuous north american dial tones 425 --- continuous european dial tones 400 --- continuous far east dial tones 480 620 0.5s/0.5s north american line busy 440 --- 0.5s/0.5s japanese line busy 480 620 0.25s/0.25s north american reorder tones 440 480 2.0s/4.0s north american audible ringing 480 620 0.25s/0.25s north american reorder tones f low f high digit b 3 b 2 b 1 b 0
mt3170b/71b, mt3270b /71b, mt3370b/71b data sheet 6 zarlink semiconductor inc. table 4 - recommended resonator and crystal specifications note: qm=quality factor of rlc model, i.e., 1/2p?r1c1. resonator and crystal electric equivalent circuit oscillator the mt327xb/337xb can be used in both external cloc k or two pin oscillator mode. in two pin oscillator mode, the oscillator circuit is completed by connecting either a 4.194304 mhz crystal or ceramic resonator across osc1 and osc2 pins. specifications of the ceramic resonator and cr ystal are tabulated in table 4. it is also possible to configure a number of these devices empl oying only a single oscillator crystal. the osc2 output of the first device in the chain is connected to the osc1 input of the next device. subsequent devices are connected similarly. the oscillator circuit can also be driven by an 4.194304 mhz external clock applied on pin osc 1. the osc2 pin should be left open. for mt317xb devices, the clk input is driven dire ctly by an 4.194304 mhz ex ternal digital clock. applications the circuit shown in figure 3 illustrates the use of a mt327 xb in a typical receiver application. it requires only a coupling capacitor (c1) and a crystal or ceramic resonator (x1) to complete the circuit. the mt3x70b is designed for user who wishes to tailor the guard time for specific applications. when a dtmf signal is present, the est pin will go high. an external mi crocontroller monitors est in real time for a period of time set by the user. a guard time algorithm must be implem ented such that dtmf signa ls not meeting the timing requirements are rejected. the mt3x71b uses an internal counter to provide a preset dtmf validation period. it requires no external components. the dstd output high indicates that a valid dt mf digit has been detected. the 4.194304 mhz frequency has a secondary advantage in some applications where a real time clock is required. a 22-bit counter will count 4,194,304 cycles to provi de a one second time base. parameter unit resonator crystal r1 ohms 6.580 150 l1 mh 0.359 95.355 c1 pf 4.441 15.1e-03 c0 pf 34.890 12.0 qm - 1.299e+03 101.2e+ 03 ? f % 0.2% 0.01% r1 = equivalent resistor. l1 = equivalent inductance. c1 = equivalent compliance. c0 = capacitance between electrode. l1 c1 r1 c0
mt3170b/71b, mt3270b /71b, mt3370b/71b data sheet 7 zarlink semiconductor inc. figure 3 - application circuit for mt327xb dtmf/cp input c1 x1 1 2 3 4 8 7 6 5 input osc2 osc1 v ss v dd est/dstd ack sd v dd components list: c 1 = 0.1 f 10 % x1 = crystal or resonator (4.194304 mhz) to microprocessor or microcontroller mt327xb
mt3170b/71b, mt3270b /71b, mt3370b/71b data sheet 8 zarlink semiconductor inc. ? exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings ? - voltages are with respect to v ss =0v unless otherwise stated. parameter symbol min. max. units 1 dc power supply voltage v dd -v ss 6v 2 voltage on any pin (other than supply) v i/o -0.3 6.3 v 3 current at any pin (other than supply) i i/o 10 ma 4 storage temperature t s -65 150 c 5 package power dissipation p d 500 mw recommended operating conditions - voltages are with respect to v ss =0v unless otherwise stated parameter sym. min. typ. ? max. units test conditions 1 positive power supply v dd 4.75 5.0 5.25 v 2 oscillator clock frequency f osc 4.194304 mhz 3 oscillator frequency tolerance ? f osc 0.1 % 4 operating temperature t d -40 25 85 c dc electrical characteristics - voltages are with respect to v dd =5v 5%,v ss =0v, and temperature -40 to 85 c, unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 operating supply current i dd 38ma 2 standby supply current i ddq 30 100 a pwdn=5v, ack=0v est/dstd = sd = 0v 3a input logic 1 v ih 4.0 v 3b input logic 1 (for osc1 input only) v ih 3.5 v mt327xb/mt337xb 4a input logic 0 v il 1.0 v 4b input logic 0 (for osc1 input only) v il 1.5 v mt327xb/mt337xb 5 input impedance (pin 1) r in 50 kw 6 pull-down current (pwdn, ack pins) i pd 25 ma with internal pull-down resistor of approx. 200 k ? . pwdn/ack = 5v 7 output high (source) current i oh 0.4 4.0 ma v out =v dd -0.4v 8 output low (sink) current i ol 1.0 9.0 ma v out =v ss +0.4v
mt3170b/71b, mt3270b /71b, mt3370b/71b data sheet 9 zarlink semiconductor inc. ac electrical characteristics - voltages are with respect to v dd =5v 5%, v ss =0v and temperature -40 to +85 c unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions* 1 valid input signal level (each tone of composite signal) -50 2.45 0 775 dbm mv rms 1,2,3,5,6,12 2 positive twist accept 8 db 1,2,3,4,11,12,15 3 negative twist accept 8 db 1,2,3,4,11,12,15 4 frequency deviation accept 1.5 % 2hz 1,2,3,5,12 5 frequency deviation reject 3.5 % 1,2,3,5,12,15 6 third tone tolerance -16 db 1,2,3,4,5,12 7 noise tolerance -12 db 7,9,12 8 dial tone tolerance +15 db 8,10,12 9 supervisory tones detect level (total power) -35 dbm 16 10 supervisory tones reject level -50 dbm 16 11 energy detector attack time t sa 1.0 6.5 ms 16 12 energy detector decay time t sd 325ms16 13a 13b powerdown time powerup time 10 30 50 ms ms ms iddq 100 a mt3170b/3370b mt3171b/3371b note 14 14 tone present detect time (est logic output) t dp 3 13 20 ms mt3x70b 15 tone absent detect time (est logic output) t da 3 15 ms mt3x70b 16 tone duration accept (dstd logic output) t rec 40 ms mt3x71b 17 tone duration reject (dstd logic output) t rec 20 ms mt3x71b
mt3170b/71b, mt3270b /71b, mt3370b/71b data sheet 10 zarlink semiconductor inc. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing * test conditions 1. dbm refers to a reference power of 1 mw delivered into a 600 ohms load. 2. data sequence consists of all dtmf digits. 3. tone on = 40 ms, tone off = 40 ms. 4. signal condition consists of nominal dtmf frequencies. 5. both tones in composite signal have an equal amplitude. 6. tone pair is deviated by 1.5% 2 hz. 7. bandwidth limited (0-3 khz) gaussian noise. 8. precise dial tone frequencies are 350 hz and 440 hz ( 2%). 9. referenced to lowest level frequency component in dtmf signal. 10. referenced to the minimum valid accept level. 11. both tones must be within valid input signal range. 12. external guard time for mt3x70b = 20 ms. 13. timing parameters are measured with 70pf load at sd output. 14. time duration between pwdn pin changes from ?1? to ?0? and est/dstd becomes active. 15. guaranteed by design and characterization. not subject to production testing. 16. value measured with an applied tone of 450 hz. 18 interdigit pause accept (dstd logic output) t id 40 ms mt3x71b 19 interdigit pause reject (dstd logic output) t do 20 ms mt3x71b 20 data shift rate 40-60% duty cycle f ack 1.0 3.0 mhz 13,15 21 propagation delay (ack to data bit) t pad 100 140 ns 1mhz f ack , 13,15 22 data hold time (ack to sd) t dh 30 50 ns 13,15 ac electrical characteristics - voltages are with respect to v dd =5v 5%, v ss =0v and temperature -40 to +85 c unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions*
mt3170b/71b, mt3270b /71b, mt3370b/71b data sheet 11 zarlink semiconductor inc. figure 4 - timing diagram figure 5 - ack to sd timing input est (mt3x70b) dstd (mt3x71b) ack sd dtmf tone #n t dp t rec t do dtmf tone #n + 1 dtmf tone #n + 1 input signal t da t rec t id lsb msb b 0 b 1 b 2 b 3 b 0 b 1 b 2 b 3 t sa t sd input signal envelope lsb msb t do t id - maximum allowable dropout during valid dtmf signals. (mt3x7xb). t rec t rec t da t dp t sa t sd - minimum time between valid dtmf signals (mt3x71b). - maximum dtmf signal duration not detected as valid (mt3x7xb). - minimum dtmf signal duration requi red for valid recognition (mt3x71b). - time to detect the absence of valid dtmf signals (mt3x70b). - time to detect the presence of valid dtmf signals (mt3x70b). - supervisory tone integrator attack time (mt3x7xb). - supervisory tone integrator decay time (mt3x7xb). est/dstd ack sd v ih v il v ih v il 1/ f ack t pad t dh b 0 b 1 b 2 b 3 msb dtmf energy detect lsb dtmf energy detect

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